R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1179

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Quantity
Price
Company:
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2)
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data,
and frame length = 16 bits
(3)
Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data,
and frame length = 64 bits
SIOF_SYNC
SIOF_RXD
SIOF_SCK
SIOF_TXD
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
8-bit Monaural Data (2)
16-bit Monaural Data
Specifications:
Specifications:
Figure 22.14 Transmit and Receive Timing (8-Bit Monaural Data (2))
Figure 22.15 Transmit and Receive Timing (16-Bit Monaural Data)
L-channel data
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
1-bit delay
Slot No.0
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
1-bit delay
L-channel data
Slot No.0
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
Slot No.1
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
1 frame
1 frame
Slot No.1
FL[3:0] = 0100 (frame length: 16 bits)
TDRE = 0,
RDRE = 0,
CD1E = 0,
Slot No.2
FL[3:0] = 1101 (frame length: 64 bits)
TDRE = 0,
RDRE = 0,
CD1E = 0,
Rev.1.00 Jan. 10, 2008 Page 1147 of 1658
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
22. Serial I/O with FIFO (SIOF)
Slot No.3
REJ09B0261-0100
SYNCDL = 1
SYNCDL = 1

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