R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 344

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
(5)
INT2MSKCR is a 32-bit write-only register that clears the masking set in the interrupt mask
register. When the corresponding bit in this register is set to 1, the interrupt source masking is
cleared. These bits are always read as 0.
Table 10.10 shows the correspondence between bits in INT2MSKCR and interrupt masking that
are cleared.
Table 10.10 Correspondence between Bits in INT2MSKCR and Interrupt Masking that Are
Rev.1.00 Jan. 10, 2008 Page 312 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to
29
28
27
26
25
24
23
22
21
20
19
R/W:
R/W:
Interrupt Mask Clear Register (INT2MSKCR)
Bit:
Bit:
Initial
Value R/W Source
All 0
0
0
0
0
0
0
0
0
0
0
R/W
31
15
⎯
R
0
0
Cleared
R
R/W GDTA
R/W DU
R/W SSI channel 1
R/W SSI channel 0
R/W GPIO
R/W FLCTL
R/W MMCIF
R/W HSPI
R/W SIOF
R/W PCIC (5)
R/W
30
⎯
14
R
0
0
Reserved
R/W
29
⎯
13
R
0
0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
The write value should always be 0.
Clears the GDTA interrupt masking
masking
masking
Clears the GPIO interrupt masking
Clears the FLCTL interrupt masking
Clears the MMCIF interrupt
masking
Clears the HSPI interrupt masking
Clears the SIOF interrupt masking
Clears the PCIERR and PCIPWD3
to PCIPWD0 interrupts masking
Function
These bits are always read as 0.
Clears the DU interrupt masking
Clears the SSI channel 1 interrupt
Clears the SSI channel 0 interrupt
R/W
R/W
26
10
0
0
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
Description
Clears interrupt
masking for each on-
chip peripheral module
[When written]
0: Invalid
1: Clears interrupt
[When read]
Always 0
masking
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0