R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 409

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11.4.4
CSnWCR (n = 0 to 6) are 32-bit readable/writable registers that specify the number of wait cycles
to be inserted for areas 0 to 6, the number of wait cycles to be inserted preceding the first data in
burst memory access, the address setup time, which is the time from the point at which the output
of address for access is started until assertion of the read/write strobe signal, and the number of
cycles to be inserted as the data hold time from negation of the write strobe signal.
CSnWCR is initialized to H'7777 770F by a power-on reset, but it is not initialized by a manual
reset.
Initial value:
Initial value:
Bit
31
30 to 28 ADS
R/W:
R/W:
BIt:
BIt:
CSn Wait Control Register (CSnWCR)
Bit Name
⎯
31
15
⎯
⎯
R
R
0
0
R/W
R/W
30
14
1
1
WTS
ADS
R/W
R/W
29
13
1
1
Initial
Value
0
111
R/W
R/W
28
12
1
1
R/W
R/W
R
R/W
27
⎯
11
⎯
R
0
0
R/W
R/W
26
10
1
1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Address Setup Cycle
These bits specify the number of cycles to be inserted
as the address setup time with respect to CSn
assertion. (Only valid when the SRAM interface, byte
control SRAM interface, or burst ROM interface is
selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
WTH
ADH
R/W
R/W
25
1
9
1
R/W
R/W
24
1
8
1
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 377 of 1658
R/W
R/W
22
1
6
0
11. Local Bus State Controller (LBSC)
RDS
BSH
R/W
R/W
21
1
5
0
R/W
R/W
20
1
4
0
R/W
19
⎯
R
0
3
1
REJ09B0261-0100
R/W
R/W
18
1
2
1
IW[3:0]
RDH
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1