R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1482

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

28. General Purpose I/O Ports (GPIO)
28.3.2
To input the data via the GPIO port, write B'10 or B'11 to the corresponding two bits in port
control registers (PACR to PRCR). B’10 should be written when the pull-up MOS is off, and B'11
when the pull-up MOS is on. The input data to each port can be read out from the corresponding
bit in port data registers (PADR to PRCR).
In this case, for each input port, the settings of port pull-up control registers (PEPUPR, PHPUPR,
PJPUPR, PKPUPR, PLPUPR, PMPUPR, and PNPUPR), peripheral module select register 1
(P1MSELR), peripheral module select register 2 (P2MSELR), and bus-mode pin (MODE11 and
MODE12) are invalid.
Figure 28.2 shows an example of operation timing diagram when port A is used as an input port.
The input data from each port can be read out from corresponding port data register after the 2nd
rising edge of the peripheral clock (Pck).
Rev.1.00 Jan. 10, 2008 Page 1450 of 1658
REJ09B0261-0100
Port Input function
CLKOUT
Peripheral clock (Pck)
Port A data register
PA7 to PA0
(D63/AD31 to D56/AD24)
Figure 28.2 Port A Data Input Timing Diagram
Data
Data