R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1144
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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22. Serial I/O with FIFO (SIOF)
22.3.7
SISTR is a 16-bit readable/writable register that indicates the SIOF state. Each bit in this register
becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1.
Rev.1.00 Jan. 10, 2008 Page 1112 of 1658
REJ09B0261-0100
Initial value:
Bit
15
14
13
R/W:
BIt:
Status Register (SISTR)
Bit Name
⎯
TCRDY
TFEMP
15
—
R
0
TCRDY
14
R
0
TFEMP
13
R
0
Initial
Value
0
0
0
TDREQ
12
R
0
R/W
R
R
R
11
—
R
0
RCRDY
10
R
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Transmit Control Data Ready
0: Indicates that writing to SITCR is disabled
1: Indicates that writing to SITCR is enabled
•
•
•
•
Transmit FIFO Empty
0: Indicates that transmit FIFO is not empty
1: Indicates that transmit FIFO is empty
•
•
•
RFFUL
R
9
0
If SITCR is written to when this bit is cleared to 0,
SITCR is overwritten to and the previous contents of
SITCR are not output from the SIOF_TXD pin.
This bit is valid when the TXE bit in SITCR is set to
1.
This bit indicates the SIOF state. If SITCR is written
to, this bit is automatically cleared to 0.
To enable the issuance of this interrupt source, set
the TCRDYE bit in SIIER to 1.
This bit is valid when the TXE bit in SICTR is 1.
This bit indicates the SIOF state. If SITDR is written
to, this bit is automatically cleared to 0.
To enable the issuance of this interrupt source, set
the TFEMPE bit in SIIER to 1.
RDREQ
R
8
0
—
R
7
0
—
R
6
0
SAERR
R/W
5
0
FSERR
R/W
4
0
TFOVF
R/W
3
0
TFUDF
R/W
2
0
RFUDF
R/W
1
0
RFOVF
R/W
0
0
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