R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1650
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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32. Electrical Characteristics
32.3.17 FLCTL Module Signal Timing
Table 32.22 NAND-Type Flash Memory Interface Timing
Notes: 1. t
Rev.1.00 Jan. 10, 2008 Page 1618 of 1658
REJ09B0261-0100
Item
Command issue setup time
Command issue hold time
Data output setup time
Data output hold time
Command to address transition time 1 t
Command to address transition time 2 t
FWE cycle time
FWE low pulse width
FWE high pulse width
Address to ready/busy transition time t
Ready/busy to data read transition
time 1
Ready/busy to data read transition
time 2
FSC cycle time
FSC high pulse width
FSC low pulse width
Read data setup time
Read data hold time
Data write setup time
Command to status read transition
time
Command output off to status read
transition time
Status read setup time
2. t
pcyc
fcyc
is the period of one FLCTL clock (Fck) cycle.
is the period of one peripheral clock (Pck) cycle.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NCDS
NCDH
NDOS
NDOH
NCDAD1
NCDAD2
NWC
NWP
NWH
NADRB
NRBDR1
NRBDR2
NSCC
NSPH
NSP
NRDS
NRDH
NDWS
NCDSR
NCDFSR
NSTS
Min.
2 × t
1.5 × t
0.5 t
0.5 t
1.5 × t
2 × t
t
0.5 t
0.5 t
—
1.5 × t
32 × t
t
0.5 × t
0.5 × t
24
5
32 × t
4 × t
3.5 × t
2.5 × t
fcyc
fcyc
−5
fcyc
fcyc
fcyc
fcyc
fcyc
fcyc
fcyc
pcyc
pcyc
fcyc
fcyc
fcyc
fcyc
fcyc
fcyc
fcyc
−10
−10
−5
−5
−10
−10
−10
−10 —
−10 —
−10 —
−5
−5
−10
Max.
—
—
—
—
—
—
—
32 × t
—
—
—
—
—
—
—
—
—
pcyc
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
32.67, 32.71
32.67, 32.68,
32.70, 32.71
32.67, 32.68
32.68
32.68, 32.70
32.67, 32.68,
32.70, 32.71
32.68, 32.70
32.68, 32.69
32.69
32.69, 32.71
32.70
32.71
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