R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1146

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1114 of 1658
REJ09B0261-0100
Bit
9
8
7, 6
Bit Name
RFFUL
RDREQ
⎯
Initial
Value
0
0
All 0
R/W
R
R
R
Description
Receive FIFO Full
0: Receive FIFO not full
1: Receive FIFO full
•
•
•
Receive Data Transfer Request
0: Indicates that the size of valid space in the receive
1: Indicates that the size of valid space in the receive
A receive data transfer request is issued when the valid
space in the receive FIFO exceeds the value specified
by the RFWM bit in SIFCTR.
When using receive data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, this bit is set to 1 again by the SIOF.
•
•
•
Reserved
These bits are always read as 0. The write value should
always be 0.
FIFO does not exceed the size specified by the
RFWM bit in SIFCTR.
FIFO exceeds the size specified by the RFWM bit in
SIFCTR.
This bit is valid when the RXE bit in SICTR is 1.
This bit indicates the state of the SIOF. If SIRDR is
read from, this bit is automatically cleared to 0.
To enable the issuance of this interrupt source, set
the RFFULE bit in SIIER to 1.
This bit is valid when the RXE bit in SICTR is 1.
This bit indicates a state; if the size of valid data
space in the receive FIFO is less than the size
specified by the RFWM bit in SIFCTR, this bit is
automatically cleared to 0.
To enable the issuance of this interrupt source, set
the RDREQE bit in SIIER to 1.