R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 433

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11. Local Bus State Controller (LBSC)
For the number of bus cycles, 0 to 25 wait cycles inserted can be selected by CS4WCR.
When the burst ROM interface is used, the number of a burst pitch is selectable in the range from
0 to 7 with the BW bits in CS4BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(when no cycles are inserted, the RDY signal is ignored.)
The setup/hold time of the address, the assert delay cycle of the read/write strobe signals for CS4
assertion and the CS4 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS4WCR. The BS hold cycles can be set to 1 or 2 when the RDS
bits in CS4WCR are not 000 in reading and the WTS bits in CS4WCR are not 000 in writing.
(6)
Area 5
Area 5 is an area where bits 28 to 26 in the local bus address are 101.
When the SRAM or burst ROM interface is used, a bus width of 8, 16, 32, or 64 bits is selectable
by bits SZ in CS5BCR. When the MPX interface is used, a bus width of 32 bits should be selected
by bits SZ in CS5BCR. When the PCMCIA interface is used, select a bus width of 8 or 16 bits
with SZ in CS5BCR. For details, see section 11.3.2, Memory Bus Width.
While the SRAM interface is used, the CS5 signal is asserted when area 5 is accessed. The RD
signal, which can be used as OE, and write control signals WE0 to WE7 are also asserted. While
the PCMCIA interface is used, the CE1A and CE2A signals, the RD signal, (which can be used as
OE), the WE0, WE1, WE2, and WE3 signals, (which can be used as, REG, WE, IORD, and
IOWR, respectively) are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS5WCR can be selected.
When the burst ROM interface is used, the number of a burst pitch is selectable the range from 0
to 7 with the BW bits in CS5BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(when no cycles are inserted, the RDY signal is ignored.)
The setup/hold time of the address, the assert delay cycle of the read/write strobe signals for CS5
assertion and the CS5 negate delay cycle for the read/write strobe signals negation can be set in
the range from 0 to 7 cycles by CS5WCR. The BS hold cycles can be set to 1 or 2 when the RDS
bits in CS5WCR are not 000 in reading and the WTS bits in CS5WCR are not 000 in writing.
For the PCMCIA interface, the setup/hold time of the address, CE1A and CE2A to the read/write
strobe signal can be specified in the range from 0 to 15 cycles by bits TEDA/B and TEHA/B in
Rev.1.00 Jan. 10, 2008 Page 401 of 1658
REJ09B0261-0100