HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 453

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 14.4 A/D Conversion Time (Single Mode)
Item
A/D start delay
Input sampling time
Total A/D conversion time
Note: Values are the number of states (tcyc).
14.4.4
The A/D converter can be started when an external trigger is input. The external trigger is input
from the ADTRG input pin when the trigger enable (TRGE) bit in the A/D control register
(ADCR) is set to 1. When the ADTRG input pin is asserted low, the A/D start (ADST) bit in the
A/D control/status register (ADCSR) is set to 1 and A/D conversion begins. All other operations
are the same as when the ADST bit is set to 1, regardless of whether the mode is single or scan.
For the timing, see figure 14.6.
14.5
The A/D converter can generate an A/D interrupt (ADI) request at the end of conversion. The ADI
request is enabled by setting the ADIE bit in ADCSR to 1, or is disabled by clearing the bit to 0.
When ADI is generated, the DMAC can be started. DMA transfers can be performed by
requesting an ADI interrupt by setting the resource select bits (RS3–RS0) in the DMA channel
control register (CHCR) of the direct memory access controller (DMAC). The ADF bit in the A/D
control/status register (ADCSR) is automatically cleared to 0 when the DMAC accesses an A/D
converter register.
Interrupts and DMA Transfer Requests
A/D Conversion Start by External Trigger Input
trigger signal
External
ADTRG
ADST
CK
Figure 14.6 External Trigger Input Timing
Symbol
t
t
t
D
SPL
CONV
Min
10
—
259
CKS = 0
Typ
—
64
—
Rev. 7.00 Jan 31, 2006 page 425 of 658
Max
17
—
266
A/D conversion
Min
6
—
131
Section 14 A/D Converter
REJ09B0272-0700
CKS = 1
Typ
—
32
—
Max
9
—
134