HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 165

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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HD6417034AFI20
Manufacturer:
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Manufacturer:
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Area 6: Area 6 is an area with address bits A26–A24 set to 110 and an address range of
H'6000000–H'6FFFFFF and H'E000000–H'EFFFFFF. Figure 8.9 shows a memory map of area 6.
In area 6, a space for which address bit A27 is 0 is allocated to address/data multiplexed I/O space
when the multiplexed I/O enable bit (IOE) of the bus control register (BCR) is 1, and to external
memory space when the IOE bit is 0. When A27 is 1, it is always external memory space.
The multiplexed I/O space is a type of external memory space but the address and data are
multiplexed and output from AD15–AD0 or AD7–AD0. The bus width is 8 bits when the A14 bit
is 0 and 16 bits when the A14 bit is 1. The A23 and A22 bits are not output and the shadow is in 4-
Mbyte units. When multiplexed I/O space is accessed, the CS6 signal is valid.
In external memory space, the bus width is 8 bits when both the A27 and A14 bits are 0 and 16
bits when the A27 bit is 0 and the A14 bit is 1. When the A27 bit is 1, it is always a 16-bit space.
The A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory
is accessed, the CS6 signal is valid. The external memory space has a long wait function so
between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle
using the area 6 long wait insertion bits (A6LW1 and A6LW0) in WCR3.
H'6000000
H'63FFFFF
H'6400000
H'67FFFFF
H'6800000
H'6BFFFFF
H'6C00000
H'6FFFFFF
Logical address
8 or 16-bit
Shadow
Shadow
Shadow
Shadow
space
space
Figure 8.9 Memory Map of Area 6
• IOE = 1:
• A14 = 0: 8-bit space
• Valid addresses
• CS6 valid
• Long wait function
Multiplexed
or external
(4 Mbytes)
I/O space
address/data
multiplexed I/O
space;
IOE = 0: external
memory space
A14 = 1: 16-bit space
A21–A0 (A23 and
A22 not output)
memory
space
Actual
space
H'E000000
H'E3FFFFF
H'E400000
H'E7FFFFF
H'E800000
H'EBFFFFF
H'EC00000
H'EFFFFFF
Rev. 7.00 Jan 31, 2006 page 137 of 658
Section 8 Bus State Controller (BSC)
Logical address
16-bit space
Shadow
Shadow
Shadow
Shadow
space
• Valid
• CS6 valid
• Long wait
(4 Mbytes)
addresses
A21–A0 (A23
and A22 not
output)
function
External
memory
Actual
space
space
REJ09B0272-0700

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