HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 350

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Programmable Timing Pattern Controller (TPC)
11.2.5
NDERA is an eight-bit read/write register that enables TPC output groups 1 and 0 (TP7–TP0) on a
bit-by-bit basis.
When the bits enabled for TPC output by NDERA generate the ITU compare match selected in the
TPC output control register, the value of the next data register A (NDRA) is automatically
transferred to the corresponding PBDR bits and the output value is updated. For disabled bits,
there is no transfer and the output value does not change. NDERA is initialized to H'00 by a reset.
It is not initialized in standby mode.
Bits 7–0—Next Data Enable 7–0 (NDER7–NDER0): NDER7–NDER0 select enabling/disabling
for TPC output groups 1 and 0 (TP7–TP0) in bit units.
Bit 7–0:
NDER7–NDER0
0
1
11.2.6
NDERB is an eight-bit read/write register that enables TPC output groups 3 and 2 (TP15–TP8) on
a bit-by-bit basis.
When the bits enabled for TPC output by NDERB generate the ITU compare match selected in the
TPC output control register, the value of the next data register B (NDRB) is automatically
transferred to the corresponding PBDR bits and the output value is updated. For disabled bits,
there is no transfer and the output value does not change. NDERB is initialized to H'00 by a reset.
It is not initialized in standby mode.
Rev. 7.00 Jan 31, 2006 page 322 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Next Data Enable Register A (NDERA)
Next Data Enable Register B (NDERB)
Description
Disables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7–PB0 is
disabled)
Enables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7–PB0 is
enabled)
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
(Initial value)
R/W
0
0