HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 442

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 A/D Converter
14.1.4
The A/D converter includes the registers listed in table 14.2.
Table 14.2 A/D Registers
Register Name
A/D data register A (high) ADDRAH
A/D data register A (low)
A/D data register B (high) ADDRBH
A/D data register B (low)
A/D data register C (high) ADDRCH
A/D data register C (low)
A/D data register D (high) ADDRDH
A/D data register D (low)
A/D control/status
register
A/D control register
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
14.2
14.2.1
The four A/D data registers (ADDRA–ADDRD) are 16-bit read-only registers that store the
results of the A/D conversion. Each result consists of 10 bits. The first 8 bits are stored in the
upper byte of the data register corresponding to the selected channel. The last two bits are stored in
the lower byte of the data register. Bits 5–0 of the lower byte are reserved and are always read as
0. Each data register is assigned to two analog input channels (table 14.3).
The A/D data registers are always readable by the CPU. The upper byte can be read directly and
the lower byte is read via a temporary register (TEMP). See section 14.3, CPU Interface, for
details. The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Rev. 7.00 Jan 31, 2006 page 414 of 658
REJ09B0272-0700
2. Only 0 can be written in bit 7, to clear the flag.
Configuration of A/D Registers
Register Descriptions
A/D Data Registers A–D (ADDRA–ADDRD)
details on the register addresses, see section 8.3.5, Area Descriptions.
Abbreviation R/W
ADDRAL
ADDRBL
ADDRCL
ADDRDL
ADCSR
ADCR
R
R
R
R
R
R
R
R
R/(W) *
R/W
2
Initial Value Address *
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'7F
H'05FFFEE0
H'05FFFEE1
H'05FFFEE2
H'05FFFEE3
H'05FFFEE4
H'05FFFEE5
H'05FFFEE6
H'05FFFEE7
H'05FFFEE8
H'05FFFEE9
1
Access Size
8, 16
16
8, 16
16
8, 16
16
8, 16
16
8, 16
8, 16