HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 40

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Notes: 1. Use prohibited in the SH7032 and SH7034 ROM-less versions.
Rev. 7.00 Jan 31, 2006 page 12 of 658
REJ09B0272-0700
Type
Operating
mode
control
Interrupts NMI
Address
bus
Data bus AD15–
2. Can be used in the SH7034 PROM version.
Symbol
MD2,
MD1,
MD0
IRQ0–
IRQ7
IRQOUT 63
A21–A0 47–44, 42,
AD0
DPH
DPL
Pin No.
(PRQP0112
JA-A)
82, 81, 80
66–69, 111,
112, 1, 2
41, 39–32,
30–23
21–16, 14,
13, 11–4
65
64
76
Pin No.
(PTQP0120
LA-A)
87, 86, 85
81
71–74, 118,
119, 2, 3
68
50–47, 45,
44, 42–35,
33, 32,
29–24
22–17, 15,
14, 12–5
70
69
I/O Name and Function
I
I
I
O
O
I/O Data bus: 16-bit bidirectional data bus that is
I/O Upper data bus parity: Parity data for D15–D8.
I/O Lower data bus parity: Parity data for D7–D0.
Mode select: Selects the operating mode. Do
not change these inputs while the chip is
operating. The following table lists the possible
operating modes and their corresponding
MD2–MD0 values.
MD2 MD1 MD0
0
0
0
0
1
1
1
1
Nonmaskable interrupt: Nonmaskable interrupt
request signal. The rising or falling edge can be
selected for signal detection.
Interrupt request 0–7: Maskable interrupt
request signals. Level input or edge-triggered
input can be selected.
Slave interrupt request output: Indicates
occurrence of an interrupt while the bus is
released.
Address bus: Outputs addresses.
multiplexed with the lower 16 bits of the
address bus.
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Operating
Mode
MCU
mode
(Reserved)
PROM
mode *
2
On-Chip
ROM
Disabled 8 bits
Enabled *
1
Bus
Size in
Area 0
16 bits

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