HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 412

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
Serial transmit data is transmitted in the following order from the TxD pin:
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
Rev. 7.00 Jan 31, 2006 page 384 of 658
REJ09B0272-0700
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI
requests a transmit-data-empty interrupt (TXI) at this time.
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
d. Stop bit: one or two 1-bits (stop bits) are output.
e. Mark state: output of 1-bits continues until the start bit of the next transmit data.
data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then
continues output of 1-bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
SCR is set to 1, a transmit-end interrupt (TEI) is requested.
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.