HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 131

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.1
The bus state controller (BSC) divides address space and outputs control signals for all kinds of
memory and peripheral chips. BSC functions enable the chip to be connected directly to DRAM,
SRAM, ROM, and peripheral chips without the use of external circuits, simplifying system design
and allowing high-speed data transfer in a compact system.
8.1.1
The BSC has the following features:
Address space is divided into eight areas
Direct interface to DRAM
Access control for all memory and peripheral chips
Parallel execution of external writes etc. with internal access (warp mode)
Supports parity check and generation for data bus
A maximum 4-Mbyte linear address space for each of eight areas, 0–7 (area 1 can be up to
16-Mbyte linear space when set for DRAM). (The space that can actually be used varies
with the type of memory connected.)
Bus width (8 bits or 16 bits) can be selected by access address
On-chip ROM and RAM is accessed in one cycle (32 bits wide)
Wait states can be inserted using the WAIT pin
Wait state insertion can be controlled by software. Register settings can be used to specify
the insertion of 1–4 cycles for areas 0, 2, and 6 (long wait function)
The type of memory connected can be specified for each area
Outputs control signals for accessing the memory and peripheral chips connected to the
area
Multiplexes row/column addresses according to DRAM capacity
Two types of byte access signals (dual-CAS system and dual-WE system)
Supports burst operation (high-speed page mode)
Supports CAS-before-RAS refresh and self-refresh
Address/data multiplex function
Odd parity/even parity selectable
Interrupt request generated for parity error (PEI interrupt request signal)
Features
Overview
Section 8 Bus State Controller (BSC)
Rev. 7.00 Jan 31, 2006 page 103 of 658
Section 8 Bus State Controller (BSC)
REJ09B0272-0700