HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 108

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Interrupt Controller (INTC)
5.5
Table 5.5 shows the interrupt response time, which is the time from the occurrence of an interrupt
request until interrupt exception handling starts and fetching of the first instruction of the interrupt
handling routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is accepted.
Table 5.5
Item
Interrupt priority decision
and comparison with SR
mask bit
Wait for completion of
sequence currently being
executed by CPU
Time from interrupt
exception handling
(saving PC and SR and
fetching vector address)
until fetching of first
instruction of interrupt
handling routine starts
Interrupt
response
Notes: m1–m4 are the number of states needed for the following memory accesses:
Rev. 7.00 Jan 31, 2006 page 80 of 658
REJ09B0272-0700
m1: SR save cycle (longword write)
m2: PC save cycle (longword write)
m3: Vector address read cycle (longword read)
m4: Fetch start instruction of interrupt handling routine
Interrupt Response Time
Interrupt Response Time
Minimum
Maximum
Total
NMI or On-Chip
Interrupt
2
X (≥ 0)
5 + m1 + m2 + m3
7 + m1 + m2 + m3
10
11 + 2(m1 + m2 +
m3) + m4
Number of States
IRQ
3
8 + m1 + m2 + m3
11
12 + 2(m1 + m2 +
m3) + m4
Notes
The longest sequence is the
interrupt or address error
exception handling
sequence: X = 4 + m1 + m2
+ m3 + m4. If an interrupt-
masking instruction follows,
however, the time may be
longer.
0.50–0.55 µs at 20 MHz
(m1 = m2 = m3 = m4 = 1)
0.90–0.95 µs at 20 MHz