HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 386

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
13.2.5
The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write to SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Communication Mode (C/A A A A ): C/A selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7: C/A A A A
0
1
Bit 6—Character Length (CHR): CHR selects seven-bit or eight-bit data in asynchronous mode.
In synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
0
1
Bit 5—Parity Enable (PE): PE selects whether to add a parity bit to transmit data and check the
parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added
nor checked, regardless of the PE setting.
Bit 5: PE
0
1
Rev. 7.00 Jan 31, 2006 page 358 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Serial Mode Register
Description
Asynchronous mode
Synchronous mode
Description
Eight-bit data
Seven-bit data. When seven-bit data is selected, the MSB (bit 7) of the transmit
data register is not transmitted.
Description
Parity bit not added or checked
Parity bit added and checked. When PE is set to 1, an even or odd parity bit is
added to transmit data, depending on the parity mode (O/E) setting. Receive
data parity is checked according to the even/odd (O/E) mode setting.
R/W
C/A
7
0
CHR
R/W
6
0
R/W
PE
5
0
R/W
O/E
4
0
STOP
R/W
3
0
R/W
MP
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKS0
R/W
0
0