HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 244

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Direct Memory Access Controller (DMAC)
9.3.6
The DMA transfer ending conditions differ for individual channel ending and ending on all
channels together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (TCR) is 0, or when the DE bit in the
channel’s CHCR is cleared to 0.
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when 1) the
NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or 2) when the DME bit
in DMAOR is cleared to 0.
Rev. 7.00 Jan 31, 2006 page 216 of 658
REJ09B0272-0700
When TCR is 0: When the TCR value becomes 0 and the corresponding channel's DMA
transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has
been set, a DMAC interrupt (DEI) request is sent to the CPU.
When DE in CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR. The TE bit is not set when this happens.
Transfers ending when the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or
DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop
their transfers. SAR, DAR, and TCR are all updated by the transfer immediately preceding the
halt. The TE bit is not set. To resume transfer after NMI interrupt exception handling or
address error exception handling, clear the appropriate flag bit to 0. When a channel’s DE bit is
then set to 1, the transfer on that channel will restart. To avoid restarting transfer on a
particular channel, keep its DE bit cleared to 0. In dual address mode, DMA transfer will be
halted after the completion of the write cycle that follows the initial read cycle in which the
address error occurs. SAR, DAR, and TCR are updated by the final transfer.
Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in
DMAOR forcibly aborts transfer on all channels at the end of the current cycle. The TE bit is
not set.
DMA Transfer Ending Conditions