HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 251

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.1
The SuperH microcomputer has an on-chip 16-bit integrated timer pulse unit (ITU) with five 16-
bit timer channels.
10.1.1
ITU features are listed below:
Can process a maximum of twelve different pulse outputs and ten different pulse inputs.
Has ten general registers (GR), two per channel, that can be set to function independently as
output compare or input capture registers.
Selection of eight counter input clock sources for all channels
All channels can be set for the following operating modes:
Channel 2 can be set to phase counting mode: Two-phase encoder output can be counted
automatically.
Channels 3 and 4 can be set in the following modes:
Buffer operation: Input capture registers can be double-buffered. Output compare registers can
be updated automatically.
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Internal clock: , /2, /4, /8,
External clock: TCLKA, TCLKB, TCLKC, TCLKD
Compare match waveform output: 0 output/1 output/selectable toggle output (0 output/1
output for channel 2)
Input capture function: Selectable rising edge, falling edge, or both rising and falling edges
Counter clearing function: Counters can be cleared by a compare match or input capture.
Synchronizing mode: Two or more timer counters (TCNT) can be written to
simultaneously. Two or more timer counters can be simultaneously cleared by a compare
match or input capture. Counter synchronization functions enable synchronized
input/output.
PWM mode: PWM output can be provided with any duty cycle. When combined with the
counter synchronizing function, enables up to five-phase PWM output.
Reset-synchronized PWM mode: By combining channels 3 and 4, 3-phase PWM output is
possible with positive and negative waveforms .
Complementary PWM mode: By combining channels 3 and 4, 3-phase PWM output is
possible with non-overlapping positive and negative waveforms.
Overview
Features
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Rev. 7.00 Jan 31, 2006 page 223 of 658
REJ09B0272-0700