ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 83

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

10.2
10.2.1
7647G–AVR–09/11
External Interrupt Control Register A – EICRA
External Interrupt Mask Register – EIMSK
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 7..0 – ISC31, ISC30 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and
the corresponding interrupt mask in the EIMSK is set. The level and edges on the external
pins that activate the interrupt are defined in
asynchronously. The value on the INT3:0 pins are sampled before detecting edges. If edge or
toggle interrupt is selected, pulses that last longer than one clock period will generate an inter-
rupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock
frequency can be lower than XTAL frequency if the XTAL divider is enabled. If low level inter-
rupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-
rupt request as long as the pin is held low.
Table 10-1.
Note:
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 3..0 – INT3 - 0: External Interrupt Request 3:0 Enable
When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in
the External Interrupt Control Register A - EICRA defines whether the external interrupt is acti-
vated on rising or falling edge or level sensed. Activity on any of these pins will trigger an
interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ISCn1
0
0
1
1
1. n = 3, 2, 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are
changed.
ISCn0
Interrupt Sense Control
ISC31
R/W
0
1
0
1
7
0
R
7
–
0
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge between two samples of INTn generates an interrupt
request.
The rising edge between two samples of INTn generates an interrupt
request.
ISC30
R/W
6
0
R
6
–
0
ISC21
R/W
5
0
R
5
–
0
Atmel ATmega16/32/64/M1/C1
(1)
ISC20
R/W
4
0
R
4
–
0
Table
ISC11
R/W
10-1. Edges on INT3..INT0 are registered
INT3
3
0
R
3
0
ISC10
R/W
INT2
2
0
R
2
0
ISC01
R/W
INT1
R/W
1
0
1
0
ISC00
R/W
INT0
R/W
0
0
0
0
EICRA
EIMSK
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