ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 205

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

17.3
17.3.1
17.3.2
7647G–AVR–09/11
LIN Protocol
Master and Slave
Frames
BREAK
Break Delimiter
Field
HEADER
A LIN cluster consists of one master task and several slave tasks. A master node contains the
master task as well as a slave task. All other nodes contain a slave task only.
Figure 17-1. LIN cluster with one master node and “n” slave nodes
The master task decides when and which frame shall be transferred on the bus. The slave
tasks provide the data transported by each frame. Both the master task and the slave task are
parts of the Frame handler
A frame consists of a header (provided by the master task) and a response (provided by a
slave task).
The header consists of a BREAK and SYNC pattern followed by a PROTECTED IDENTIFIER.
The identifier uniquely defines the purpose of the frame. The slave task appointed for provid-
ing the response associated with the identifier transmits it. The response consists of a DATA
field and a CHECKSUM field.
Figure 17-2. Master and slave tasks behavior in LIN frame
The slave tasks waiting for the data associated with the identifier receives the response and
uses the data transported after verifying the checksum.
Figure 17-3. Structure of a LIN frame
Slave Task 1
Slave Task 2
SYNC
Master Task
Field
master node
master task
slave task
PROTECTED
IDENTIFIER
HEADER
Response Space
Field
FRAME SLOT
RESPONSE
DATA-0
Atmel ATmega16/32/64/M1/C1
slave node
slave task
LIN bus
Field
1
RESPONSE
Each byte field is transmitted as a serial byte, LSB first.
DATA-n
HEADER
Inter-Byte Space
Field
slave node
slave task
CHECKSUM
n
RESPONSE
Field
Inter-Frame Space
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