ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 37

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

5.9
5.10
7647G–AVR–09/11
Clock Output Buffer
System Clock Prescaler
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in
Table 5-9.
When applying an external clock, it is required to avoid sudden changes in the applied clock
frequency to ensure stable operation of the MCU. A variation in frequency of more than 2%
from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure
that the MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. Refer to
page 37
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode
is suitable when chip clock is used to drive other circuits on the system. The clock will be out-
put also during reset and the normal operation of I/O pin will be overridden when the fuse is
programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock
that is output (CKOUT Fuse programmed).
The ATmega16/32/64/M1/C1 system clock can be divided by setting the Clock Prescale Reg-
ister – CLKPR. This feature can be used to decrease power consumption when the
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher
than neither the clock frequency corresponding to the previous setting, nor the clock frequency
corresponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence,
it is not possible to determine the state of the prescaler - even if it were readable, and the
exact time it takes to switch from one clock division to the other cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before
the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
SUT1..0
Table
CPU
00
01
10
11
, and clk
5-9.
for details.
Power-down and Power-save
FLASH
Start-up Times for the External Clock Selection
Start-up Time from
are divided by a factor as shown in
6 CK
6 CK
6 CK
Atmel ATmega16/32/64/M1/C1
Additional Delay from
Reset (V
Reserved
14CK + 4.1 ms
14CK + 65 ms
14CK
CC
Table
= 5.0V)
5-10.
“System Clock Prescaler” on
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
I/O
, clk
ADC
37
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