ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 181

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

16.5.4
16.5.5
7647G–AVR–09/11
MOb Page
CAN Data Buffers
internal RxDcan
Figure 16-10. Acceptance Filter Block Diagram
Note:
Every MOb is mapped into a page to save place. The page number is the MOb number. This
page number is set in CANPAGE register. The other numbers are reserved for factory tests.
CANHPMOB register gives the MOb having the highest priority in CANSIT registers. It is for-
matted to provide a direct entry for CANPAGE register. Because CANHPMOB codes CANSIT
registers, it will be only updated if the corresponding enable bits (ENRX, ENTX, ENERR) are
enabled (c.f.
To preserve register allocation, the CAN data buffer is seen such as a FIFO (with address
pointer accessible) into a MOb selection.This also allows to reduce the risks of un-controlled
accesses.
There is one FIFO per MOb. This FIFO is accessed into a MOb page thanks to the CAN mes-
sage register.
The data index (INDX) is the address pointer to the required data byte. The data byte can be
read or write. The data index is automatically incremented after every access if the AINC* bit is
reset. A roll-over is implemented, after data index=7 it is data index=0.
The first byte of a CAN frame is stored at the data index=0, the second one at the data
index=1, ...
CANIDT Registers & CANCDMOB (MOb[i])
Examples:
Full filtering: to accept only ID = 0x317 in part A.
- ID MSK = 111 1111 1111
- ID TAG = 011 0001 0111
Partiel filtering: to accept ID from 0x310 up to 0x317 in part A.
- ID MSK = 111 1111 1000
- ID TAG = 011 0001 0xxx
No filtering: to accept all ID’s from 0x000 up to 0x7FF in part A.
- ID MSK = 000 0000 0000
- ID TAG = xxx xxxx xxxx
ID & RB
Figure
14(33)
16-14).
Rx Shift Register (internal)
ID & RB
RTRTAG
Enable
Write
14(33)
13(31) - RB excluded
IDE
RTR
Atmel ATmega16/32/64/M1/C1
b
b
b
b
b
b
=
IDE
RB excluded
IDMSK
13(31)
1
CANIDM Registers (MOb[i])
13(31)
RTRMSK
IDEMSK
Hit MOb[i]
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