ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 274

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

21.4.2.2
274
Atmel ATmega16/32/64/M1/C1
DALA = 1
To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate
value, the DAC input values which are really converted into analog signal are buffered into
unreachable registers. In normal mode, the update of the shadow register is done when the
register DACH is written.
In case DAATE bit is set, the DAC input values will be updated on the trigger event selected
through DATS bits.
In order to avoid wrong DAC input values, the update can only be done after having written
respectively DACL and DACH registers. It is possible to work on 8-bit configuration by only
writing the DACH value. In this case, update is done each trigger event.
In case DAATE bit is cleared, the DAC is in an automatic update mode. Writing the DACH reg-
ister automatically update the DAC input values with the DACH and DACL register values.
It means that whatever is the configuration of the DAATE bit, changing the DACL register has
no effect on the DAC output until the DACH register has also been updated. So, to work with
10 bits, DACL must be written first before DACH. To work with 8-bit configuration, writing
DACH allows the update of the DAC.
Bit
Read/Write
Initial Value
DAC9
DAC1
R/W
R/W
7
0
0
DAC8
DAC0
R/W
R/W
6
0
0
DAC7
R/W
R/W
5
0
0
-
DAC6
R/W
R/W
4
0
0
-
DAC5
R/W
R/W
3
0
0
-
DAC4
R/W
R/W
2
0
0
-
DAC3
R/W
R/W
1
0
0
-
DAC2
R/W
R/W
0
0
0
-
7647G–AVR–09/11
DACH
DACL