ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 159

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

7647G–AVR–09/11
The interconnection between Master and Slave CPUs with SPI is shown in
system consists of two shift Registers, and a Master clock generator. The SPI Master initiates
the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Mas-
ter and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always
shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Mas-
ter on the Master In – Slave Out, MISO, line. After each data packet, the Master will
synchronize the Slave by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing
a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the
eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end
of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set,
an interrupt is requested. The Master may continue to shift the next byte by writing it into
SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming
byte will be kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as
long as the SS pin is driven high. In this state, software may update the contents of the SPI
Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK
pin until the SS pin is driven low. As one byte has been completely shifted, the end of trans-
mission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an
interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later
use.
Figure 15-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must
be read from the SPI Data Register before the next character has been completely shifted in.
Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed
f
clkio
/4.
Atmel ATmega16/32/64/M1/C1
Figure
SHIFT
ENABLE
15-2. The
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