ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 204

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

17. LIN / UART - Local Interconnect Network Controller or UART
17.1
17.2
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UART Features
LIN Features
Atmel ATmega16/32/64/M1/C1
The LIN (Local Interconnect Network) is a serial communications protocol which efficiently
supports the control of mechatronics nodes in distributed automotive applications. The main
properties of the LIN bus are:
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LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN
are not required. The specification of the line driver/receiver needs to match the ISO9141
NRZ-standard.
If LIN is not required, the controller alternatively can be programmed as Universal Asynchro-
nous serial Receiver and Transmitter (UART).
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Single master with multiple slaves concept
Low cost silicon implementation based on common UART/SCI interface
Self synchronization in slave node
Deterministic signal transmission with signal propagation time computable in advance
Low cost single-wire implementation
Speed up to 20 Kbit/s.
Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility)
Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow
Concept” of LIN 2.1 Specification
Automatic LIN Header Handling and Filtering of Irrelevant LIN Frames
Automatic LIN Response Handling
Extended LIN Error Detection and Signaling
Hardware Frame Time-out Detection
“Break-in-data” Support Capability
Automatic Re-synchronization to Ensure Proper Frame Integrity
Fully Flexible Extended Frames Support Capabilities
Full Duplex Operation (Independent Serial Receive and Transmit Processes)
Asynchronous Operation
High Resolution Baud Rate Generator
Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames
Data Over-Run and Framing Error Detection
7647G–AVR–09/11