ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 166
ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
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15.2.6
15.3
166
Data Modes
Atmel ATmega16/32/64/M1/C1
SPI Data Register – SPDR
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
ure 15-3
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing
Table 15-5.
Figure 15-3. SPI Transfer Format with CPHA = 0
Bit
Read/Write
Initial Value
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
Table 15-2
and
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
Figure
MSB first (DORD = 0)
LSB first (DORD = 1)
CPOL Functionality
SPD7
R/W
X
7
and
15-4. Data bits are shifted out and latched in on opposite edges of the
SPD6
R/W
Table
X
6
MSB
LSB
15-3, as done below:
Sample (Falling)
SPD5
Sample (Rising)
R/W
Leading Edge
Setup (Falling)
Setup (Rising)
X
5
Bit 6
Bit 1
SPD4
R/W
X
4
Bit 5
Bit 2
SPD3
R/W
Bit 4
Bit 3
X
3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
Bit 3
Bit 4
SPD2
R/W
X
2
Bit 2
Bit 5
SPD1
R/W
1
X
Bit 1
Bit 6
SPD0
R/W
X
0
7647G–AVR–09/11
LSB
MSB
SPI Mode
Undefined
0
1
2
3
SPDR
Fig-
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