ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 123

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

13.8.4
7647G–AVR–09/11
Phase Correct PWM Mode
This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O loca-
tion is written the value written will be put into the OCRnA Buffer Register.
The OCRnA Compare Register will then be updated with the value in the Buffer Register at the
next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock
cycle as the TCNTn is cleared and the TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. How-
ever, if the base PWM frequency is actively changed (by changing the TOP value), using the
OCRnA as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COMnx1:0 to three (see
OCnx value will only be visible on the port pin if the data direction for the port pin is set as out-
put (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register
at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Regis-
ter at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000)
the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal
to TOP will result in a constant high or low output (depending on the polarity of the output set
by the COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies
only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will
have a maximum frequency of f
ture is similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and
then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and
set on the compare match while downcounting. In inverting Output Compare mode, the opera-
tion is inverted. The dual-slope operation has lower maximum operation frequency than single
slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these
modes are preferred for motor control applications.
f
OCnxPWM
=
-------------------------------------
N
f
clk_I/O
1
+
TOP
OC
n
A
Atmel ATmega16/32/64/M1/C1
= f
clk_I/O
/2 when OCRnA is set to zero (0x0000). This fea-
Table on page
130). The actual
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