ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 36

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

5.6.2
5.7
5.8
36
128 kHz Internal Oscillator
External Clock
Atmel ATmega16/32/64/M1/C1
PLL Control and Status Register – PLLCSR
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this
bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
lock.
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
To drive the device from an external clock source, XTAL1 should be driven as shown in
5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 5-4.
Table 5-8.
Bit
$29 ($29)
Read/Write
Initial Value
CKSEL3..0
0000
PLL
for Fast Peripherals. After the PLL is enabled, it takes about 100 ms for the PLL to
External Clock Drive Configuration
External Clock Frequency
R
7
–
0
R
6
–
0
External
R
5
–
0
Signal
Clock
NC
Frequency Range
0 - 16MHz
R
4
–
0
R
3
–
0
PLLF
R/W
XTAL2
XTAL1
GND
2
0
PLLE
R/W
0/1
1
PLOCK
R
0
0
7647G–AVR–09/11
PLLCSR
Figure