ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 139

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

14.5.3
14.5.3.1
7647G–AVR–09/11
Operation Mode Descriptions
One Ramp Mode (Edge-Aligned)
Figure 14-3. Cycle Presentation in Centered Mode
Figure 14-2
tered Mode is like One Ramp Mode which counts down and then up.
Notice that the update of the waveform generator registers is done regardless of ramp Mode
at the end of the PSC cycle.
Waveforms and duration of output signals are determined by parameters held in the registers
(POCRnSA, POCRnRA, POCRnSB, POCR_RB) and by the running mode. Two modes are
possible :
The following figure shows the resultant outputs PSCOUTnA and PSCOUTnB operating in
one ramp mode over a PSC cycle.
PSC Counter Value
• One Ramp Mode. In this mode, all the 3 PSCOUTnB outputs are edge-aligned and the 3
• Center Aligned Mode. In this mode, all the 6 PSC outputs are aligned at the center of the
PSCOUTnA can be also edge-aligned when setting the same values in the dedicated
registers.
In this mode, the PWM frequency is twice the Center Aligned Mode PWM frequency.
period. Except when using the same duty cycles on the 3 modules, the edges of the
outputs are not aligned. So the PSC outputs do not commute at the same time, thus the
system which is driven by these outputs will generate less commutation noise.
In this mode, the PWM frequency is twice slower than in One Ramp Mode.
and
Figure 14-3
graphically illustrate the values held in the PSC counter. Cen-
Atmel ATmega16/32/64/M1/C1
One PSC Cycle
UPDATE
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