ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 143

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

14.6.1
14.7
7647G–AVR–09/11
Overlap Protection
Value Update Synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to
LOCK configuration bit, the new whole set of values can be taken into account after the end of
the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal regis-
ters will be done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POM2, POCRnSAH/L,
POCRnRAH/L, POCRnSBH/L and POCRnRBH/L.
See these register’s description starting on
See “PSC Configuration Register – PCNF” on page 153.
Thanks to Overlap Protection two outputs on a same module cannot be active at the same
time. So it cannot generate cross conduction. This feature can be disactivated thanks to
POVEn (PSC Overlap Enable).
For ATmega16/64M1, and ATmega32M1 since rev C, the overlap protection is activated with
only one condition:
Up to rev B of ATmega32M1, the overlap protection was activated with the 2 following
conditions:
This difference can induce some behavior change between rev B & rev C of ATmega32M1,
when only one channel of a PWM pair output is active.
To avoid such behavior, it is recommended in case of using only one channel of a pwm pair,
to disable Overlap protection bit (POVENn =1).
1. POVENn=0 (PSC Module n Overlap Enable)
2. POVENn=0 (PSC Module n Overlap Enable)
3. The two channels A and B of a pwm pair n must be activated (POENnA=POENnB=
1)
Atmel ATmega16/32/64/M1/C1
page
153.
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