ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 134

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

13.10.6
13.10.7
13.10.8
134
Atmel ATmega16/32/64/M1/C1
Output Compare Register 1 B – OCR1BH and OCR1BL
Input Capture Register 1 – ICR1H and ICR1L
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers.
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on
the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input
Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the
other 16-bit registers.
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4, 3 – Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The correspond-
ing Interrupt Vector
TIFR1, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(Table 8-2 on page
R/W
R/W
R
7
0
7
0
7
–
0
(Table 8-2 on page
See “Accessing 16-bit Registers” on page 109.
R/W
R/W
See “Accessing 16-bit Registers” on page 109.
R
6
0
6
0
6
–
0
58) is executed when the ICF1 Flag, located in TIFR1, is set.
ICIE1
R/W
R/W
R/W
5
0
5
0
5
0
58) is executed when the OCF1B Flag, located in
R/W
R/W
R
4
–
0
4
0
4
OCR1B[15:8]
0
OCR1B[7:0]
ICR1[15:8]
ICR1[7:0]
R/W
R/W
R
3
–
0
3
0
3
0
OCIE1B
R/W
R/W
R/W
2
0
2
0
2
0
OCIE1A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE1
R/W
R/W
R/W
0
0
0
0
0
0
7647G–AVR–09/11
OCR1BH
OCR1BL
TIMSK1
ICR1H
ICR1L