MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 523

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.4.6
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
Section 18.3.2.1, “BDM Status Register
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Because R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in
Figure
Because the host and target are operating from separate clocks, it can take the target system up to one full
clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time
while the host measures delays from the point it actually drove BKGD low to start the bit up to one target
Freescale Semiconductor
HARDWARE
HARDWARE
FIRMWARE
FIRMWARE
18-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge.
TRACE
WRITE
WRITE
READ
READ
GO,
BDM Serial Interface
AT 16 TC/BIT
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
8 BITS
DELAY
44-BC
DELAY
64-BC
AT 16 TC/BIT
Figure 18-6. BDM Command Structure
ADDRESS
ADDRESS
16 BITS
DATA
MC9S12HZ256 Data Sheet, Rev. 2.05
COMMAND
NEXT
(BDMSTS).” This clock will be referred to as the target clock in
DATA
Figure 18-7
DELAY
32-BC
and that of target-to-host in
150-BC
DELAY
COMMAND
COMMAND
NEXT
NEXT
DATA
Chapter 18 Background Debug Module (BDMV4)
AT 16 TC/BIT
16 BITS
DATA
BC = BUS CLOCK CYCLES
TC = TARGET CLOCK CYCLES
150-BC
DELAY
Figure 18-8
COMMAND
COMMAND
NEXT
NEXT
and
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