MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 185

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.2
The clock generator creates the clocks used in the MCU (see
top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting
of the respective configuration bits.
The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The
memory blocks use the bus clock. If the MCU enters self-clock mode (see
Mode”), oscillator clock source is switched to PLLCLK running at its minimum frequency f
clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.
The core clock is twice the bus clock as shown in
one bus clock.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned
off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
Freescale Semiconductor
EXTAL
XTAL
System Clocks Generator
OSCILLATOR
Condition
Gating
PHASE
LOCK
LOOP
= Clock Gate
OSCCLK
PLLCLK
Monitor
Clock
Figure 5-17. System Clocks Generator
MC9S12HZ256 Data Sheet, Rev. 2.05
PLLSEL or SCM
1
0
1
0
SCM
Figure
STOP(PSTP,PCE),
STOP(PSTP,PRE),
WAIT(COPWAI),
WAIT(SYSWAI),
WAIT(RTIWAI),
WAIT(SYSWAI),
STOP(PSTP)
COP enable
RTI enable
STOP
STOP
5-18. But note that a CPU cycle corresponds to
SYSCLK
Figure
Chapter 5 Clocks and Reset Generator (CRGV4)
5-17). The gating condition placed on
WAIT(CWAI,SYSWAI),
2
Section 5.4.7.2, “Self-Clock
STOP
CLOCK PHASE
GENERATOR
COP
RTI
SCM
Pseudo-Stop Mode
(running during
Core Clock
Bus Clock
. The bus
Oscillator
Oscillator
Clock
Clock
185