MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 251

IC MCU 16BIT 2K FLASH 112-LQFP

MC9S12HZ128VAL

Manufacturer Part Number
MC9S12HZ128VAL
Description
IC MCU 16BIT 2K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12HZ128VAL

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12HZ128VAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12HZ128VAL
Manufacturer:
FREESCALE
Quantity:
20 000
8.4.2
The LCD32F4B driver system operation during wait mode is controlled by the LCD stop in wait
(LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD32F4B driver
system continues to operate during wait mode. If LCDSWAI is set, the LCD32F4B driver system is turned
off during wait mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4B
drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering wait
mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering
wait mode.
8.4.3
The LCD32F4B driver system operation during pseudo stop mode is controlled by the LCD run in pseudo
stop (LCDRPSTP) bit in the LCD control register 1 (LCDCR1). If LCDRPSTP is reset, the LCD32F4B
driver system is turned off during pseudo stop mode. In this case, the LCD waveform generation clocks
are stopped and the LCD32F4B drivers pull down to VSSX those frontplane and backplane pins that were
enabled before entering pseudo stop mode. If LCDRPSTP is set, the LCD32F4B driver system continues
to operate during pseudo stop mode. The contents of the LCD RAM and the LCD registers retain the
values they had prior to entering pseudo stop mode.
8.4.4
All LCD32F4B driver system clocks are stopped, the LCD32F4B driver system pulls down to VSSX those
frontplane and backplane pins that were enabled before entering stop mode. Also, during stop mode, the
contents of the LCD RAM and the LCD registers retain the values they had prior to entering stop mode.
As a result, after exiting from stop mode, the LCD32F4B driver system clocks will run (if LCDEN = 1)
and the frontplane and backplane pins retain the functionality they had prior to entering stop mode.
8.4.5
Figure 8-9
modes of operation.
Freescale Semiconductor
Duty
1/1
1/2
1/3
1/4
DUTY1
through
LCDCR0 Register
Operation in Wait Mode
Operation in Pseudo Stop Mode
Operation in Stop Mode
LCD Waveform Examples
0
1
1
0
Figure 8-13
DUTY0
1
0
1
0
show the timing examples of the LCD output waveforms for the available
BP3
OFF
OFF
OFF
BP3
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 8-8. LCD Duty and Bias
OFF
OFF
BP2
BP2
BP2
Backplanes
BP1
OFF
BP1
BP1
BP1
BP0
BP0
BP0
BP0
BP0
YES
1/1
NA
NA
NA
Bias (BIAS = 0)
Chapter 8 Liquid Crystal Display (LCD32F4BV1)
YES
1/2
NA
NA
NA
YES
YES
1/3
NA
NA
YES
1/1
NA
NA
NA
Bias (BIAS = 1)
1/2
NA
NA
NA
NA
YES
YES
YES
1/3
NA
251

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