MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 312

IC MCU 16BIT 2K FLASH 112-LQFP

MC9S12HZ128VAL

Manufacturer Part Number
MC9S12HZ128VAL
Description
IC MCU 16BIT 2K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12HZ128VAL

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12HZ128VAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12HZ128VAL
Manufacturer:
FREESCALE
Quantity:
20 000
Chapter 11 Inter-Integrated Circuit (IICV2)
11.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
11.3.2.1
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
312
Reserved
ADR[7:1]
Reset
Field
Register
7:1
0
Name
IBCR
IBDR
IBAD
IBFD
IBSR
W
R
Register Descriptions
ADR7
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
IIC Address Register (IBAD)
0
7
W
W
W
W
W
R
R
R
R
R
= Unimplemented or Reserved
ADR7
ADR6
IBEN
Bit 7
IBC7
TCF
D7
0
6
Figure 11-2. IIC Bus Address Register (IBAD)
= Unimplemented or Reserved
ADR6
IBC6
IAAS
IBIE
Table 11-1. IIC Register Summary
Table 11-2. IBAD Field Descriptions
D6
6
ADR5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
MS/SL
ADR5
IBC5
IBB
D5
5
ADR4
0
4
Description
ADR4
Tx/Rx
IBC4
IBAL
D4
4
ADR3
0
3
ADR3
TXAK
IBC3
D3
3
0
ADR2
0
2
ADR2
IBC2
RSTA
SRW
D2
2
0
Freescale Semiconductor
ADR1
ADR1
IBC1
IBIF
D1
0
1
1
0
IBSWAI
RXAK
Bit 0
IBC0
D0
0
0
0
0

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