MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 149

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.6.2
Read: Anytime. Write: Never, writes to this register have no effect.
If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled), a read
returns a 1.
If the LCD frontplane driver of the associated I/O pin is disabled (or LCD module is disabled), a read
returns the status of the associated pin.
4.3.6.3
Read: Anytime. Write: Anytime.
This register configures port pins PT[7:0] as either input or output.
If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the
corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver
is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
If the TIM module is enabled, each port pin configured for output compare is forced to be an output and
the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled,
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
If the TIM module is enabled, each port pin configured as an input capture has the corresponding Data
Direction Register bit controlling the I/O direction of the associated pin.
Freescale Semiconductor
DDRT[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRT7
PTIT7
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
u
0
7
7
= Reserved or Unimplemented
DDRT6
PTIT6
u
0
6
6
Figure 4-39. Port T Data Direction Register (DDRT)
Figure 4-38. Port T Input Register (PTIT)
Table 4-28. DDRT Field Descriptions
DDRT5
PTIT5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRT4
PTIT4
u
0
4
4
Description
u = Unaffected by reset
DDRT3
PTIT3
u
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRT2
PTIT2
u
0
2
2
DDRT1
PTIT1
u
0
1
1
DDRT0
PTIT0
u
0
0
0
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