MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 134

IC MCU 16BIT 2K FLASH 112-LQFP

MC9S12HZ128VAL

Manufacturer Part Number
MC9S12HZ128VAL
Description
IC MCU 16BIT 2K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12HZ128VAL

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12HZ128VAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12HZ128VAL
Manufacturer:
FREESCALE
Quantity:
20 000
CAN0/CAN1:
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.3
Port M is associated with Freescale’s scalable controller area network (CAN1 and CAN0) modules. Each
pin is assigned to these modules according to the following priority: CAN1/CAN0 > general-purpose I/O.
When the CAN1 module is enabled, PM[5:4] pins become TXCAN1 (transmitter) and RXCAN1
(receiver) pins for the CAN1 module. When the CAN0 module is enabled, PM[3:2] pins become TXCAN0
(transmitter) and RXCAN0 (receiver) pins for the CAN0 module. Refer to the MSCAN block description
chapter for information on enabling and disabling the CAN module.
During reset, port M pins are configured as high-impedance inputs.
4.3.3.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
4.3.3.2
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
134
Reset
Reset
W
R
W
R
Port M
Port M I/O Register (PTM)
Port M Input Register (PTIM)
0
0
7
0
0
7
= Reserved or Unimplemented
= Reserved or Unimplemented
0
0
6
0
0
6
Figure 4-17. Port M Input Register (PTIM)
Figure 4-16. Port M I/O Register (PTM)
PTIM5
MC9S12HZ256 Data Sheet, Rev. 2.05
TXCAN1
u
5
PTM5
0
5
PTIM4
RXCAN1
PTM4
u
4
0
4
u = Unaffected by reset
PTIM3
TXCAN0
PTM3
u
3
0
3
PTIM2
RXCAN0
PTM2
u
2
0
2
Freescale Semiconductor
0
0
1
0
0
1
0
0
0
0
0
0

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