MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 384

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
12.4.8.1
The MSCAN supports four interrupt vectors (see
(for details see sections from
(CANRIER),” to
12.4.8.2
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
12.4.8.3
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
12.4.8.4
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode.
WUPE (see
12.4.8.5
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs.
conditions:
384
•
•
Overrun — An overrun condition of the receiver FIFO as described in
Structures,” occurred.
CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range
(Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change,
which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
Section 12.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)
Section 12.3.2.1, “MSCAN Control Register 0
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
Description of Interrupt Operation
Transmit Interrupt
Receive Interrupt
Wake-Up Interrupt
Error Interrupt
The dedicated interrupt vector addresses are defined in the
Interrupts
Section 12.3.2.8, “MSCAN Transmitter Interrupt Enable Register
Interrupt Source
chapter.
Section 12.3.2.6, “MSCAN Receiver Interrupt Enable Register
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 12-38. Interrupt Vectors
NOTE
Table
CCR Mask
12-38), any of which can be individually masked
I bit
I bit
I bit
I bit
(CANCTL0)”) must be enabled.
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
Local Enable
Resets and
indicates one of the following
Section 12.4.2.3, “Receive
(CANTIER)”).
Freescale Semiconductor