MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 199

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Definition.” All reset sources are listed in
vector addresses and priorities.
The reset sequence is initiated by any of the following events:
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the
RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then
samples the RESET pin to determine the originating source.
fetched.
Freescale Semiconductor
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Figure
Low level is detected at the RESET pin (external reset).
Power on is detected.
Low voltage is detected.
COP watchdog times out.
Clock monitor failure is detected and self-clock mode was disabled (SCME = 0).
5-25). Because entry into reset is asynchronous it does not require a running SYSCLK.
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
Sampled RESET Pin
(64 Cycles After
Release)
1
1
1
0
COP Watchdog Reset
Clock Monitor Reset
Low Voltage Reset
Power-on Reset
External Reset
Reset Source
Table 5-14. Reset Vector Selection
MC9S12HZ256 Data Sheet, Rev. 2.05
Reset Pending
Clock Monitor
Table 5-13. Reset Summary
Table
X
0
1
0
5-13. Refer to the device overview chapter for related
NOTE
PLLCTL (CME=1, SCME=0)
COPCTL (CR[2:0] nonzero)
COP Reset
Pending
Local Enable
X
X
0
1
Table 5-14
None
None
None
POR / LVR / External Reset
Clock Monitor Reset
COP Reset
POR / LVR / External Reset
with rise of RESET pin
Chapter 5 Clocks and Reset Generator (CRGV4)
shows which vector will be
Vector Fetch
199