MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 128

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.6
Read: Anytime. Write: Anytime.
The Port AD Polarity Select Register serves a dual purpose by selecting the polarity of the active interrupt
edge as well as selecting a pull-up or pull-down device if enabled (PERADx = 1). The Port AD Polarity
Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input).
In pull-down mode (PPSADx = 1), a rising edge on a port AD pin sets the corresponding PIFADx bit. In
pull-up mode (PPSADx = 0), a falling edge on a port AD pin sets the corresponding PIFADx bit.
4.3.1.7
Read: Anytime. Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port AD.
128
PPSAD[7:0]
PIEAD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PPSAD7
PIEAD7
Polarity Select Port AD
0 A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation.
1 A pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt
Interrupt Enable Port AD
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Port AD Polarity Select Register (PPSAD)
Port AD Interrupt Enable Register (PIEAD)
0
0
7
7
generation.
PPSAD6
PIEAD6
0
0
6
6
Figure 4-8. Port AD Interrupt Enable Register (PIEAD)
Figure 4-7. Port AD Polarity Select Register (PPSAD)
Table 4-6. PPSAD Field Descriptions
PPSAD5
Table 4-7. PIEAD Field Descriptions
PIEAD5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
5
PPSAD4
PIEAD4
0
0
4
4
Description
Description
PPSAD3
PIEAD3
0
0
3
3
PPSAD2
PIEAD2
0
0
2
2
PPSAD1
PIEAD1
Freescale Semiconductor
0
0
1
1
PPSAD0
PIEAD0
0
0
0
0