pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 95

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

PEB 20550
PEF 20550
Operational Description
The CFI-standby function switches all CFI-output lines to high impedance with a single
command. Internally the device still works normally, only the output drivers are switched
off.
The number of time slots per 8-kHz frame is programmable from 2 to 128. In other words,
the CFI-data rate can range between 128 kbit/s up to 8192 kbit/s. Since the overall
switching capacity is limited to 128 time slots per direction, the number of CFI- ports also
depends on the required number of time slots: in case of 32 time slots per frame
(2048 kbit/s) for example, four highways are available, in case of 128 time slots per
frame (8192 kbit/s), only one highway is available. Usually, the number of bits per 8-kHz
frame is an integer multiple of the number of time slots per frame (1 time slot = 8 bits).
The timing characteristics at the CFI (data rate, bit shift, etc.) can be varied in a wide
range, but they are the same for each of the four CFI-ports, i.e. if a data rate of 2048 kbit/
s is selected, all four ports run at this data rate of 2048 kbit/s. It is thus not possible to
have one port used in IOM-2 line card mode (2048 kbit/s) while another port is used in
IOM-2 terminal mode (768 kbit/s)!
The clock and framing signals necessary to operate the configurable interface may be
derived either from the clock and framing signals of the PCM-interface (PDC and PFS
pins), or may be fed in directly via the DCL- and FSC-pins.
In the first case, the CFI-data rate is obtained by internally dividing down the PCM-clock
signal PDC. Several prescaler factors are available to obtain the most commonly used
data rates. A CFI reference clock (CRCL) is generated out of the PDC-clock. The PCM-
framing signal PFS is used to synchronize the CFI-frame structure. Additionally, the
EPIC-1 generates clock and framing signals as outputs to operate the connected
subscriber circuits such as layer-1 and codec filter devices. The generated data clock
DCL has a frequency equal to or twice the CFI-data rate. The generated framing signal
FSC can be chosen from a great variety of types to suit the different applications: IOM-2,
multiplexed IOM-1, SLD, etc.
Note that if PFS is selected as the framing signal source, the FSC-signal is an output
with a fixed timing relationship with respect to the CFI-data lines. The relationship
between FSC and the CFI-frame depends only on the selected FSC-output wave form
(CMD2- register). The CFI-offset function shifts both the frame and the FSC-output
signal with respect to the PFS-signal.
In the second case, the CFI-data rate is derived from the DCL-clock, which is now used
as an input signal. The DCL-clock may also first be divided down by internal prescalers
before it serves as the CFI reference clock CRCL and before defining the CFI-data rate.
The framing signal FSC is used to synchronize the CFI-frame structure.
3.5.3
Switching Functions
The major tasks of the EPIC-1 part is to dynamically switch PCM-data between the serial
PCM-interface, the serial configurable interface (CFI) and the parallel P-interface. All
possible switching paths are shown in figure 47.
Semiconductor Group
95
01.96