pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 347

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

Initialization values for the IDEC that controls the lower 4 channels of the IOM-2
interface:
IDEC
CCR
A_MODE
A_TSR
B_MODE
B_TSR
C_MODE
C_TSR
D_MODE
D_TSR
Initialization values for the IDEC that controls the upper 4 channels of the IOM-2
interface:
IDEC
CCR
A_MODE
A_TSR
B_MODE
B_TSR
C_MODE
C_TSR
D_MODE
D_TSR
The ELIC initialization is the same as for the IOM-2 application described previously in
this chapter.
Semiconductor Group
®
®
= 0000 1100B = 0C
= 0001 1100B = 1C
= 0100 1100B = 4C
= 0101 1100B = 5C
= 1000 0010B = 82
= 0000 1100B = 0C
= 0000 1100B = 0C
= 0000 1100B = 0C
= 0010 1100B = 2C
= 0000 1100B = 0C
= 0011 1100B = 3C
= 1000 0010B = A2
= 0000 1100B = 0C
= 0000 1100B = 0C
= 0000 1100B = 0C
= 0110 1100B = 6C
= 0000 1100B = 0C
= 0111 1100B = 7C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
IOM-2 mode, IOM ch. 0 - 3, double clock rate,
256 bits/frame
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. A timeslot position: D channel of IOM ch. 0
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. B timeslot position: D channel of IOM ch. 1
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. C timeslot position: D channel of IOM ch. 2
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. D timeslot position: D channel of IOM ch. 3
IOM-2 mode, IOM ch. 4-7, double clock rate,
256 bits/frame
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. A timeslot position: D channel of IOM ch. 4
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. B timeslot position: D channel of IOM ch. 5
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. C timeslot position: D channel of IOM ch. 6
uncond. trans., 16 kBit/s ch., channel and
receiver active
ch. D timeslot position: D channel of IOM ch. 7
347
Application Hints
PEB 20550
PEF 20550
01.96