pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 149

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

4.6.17 Synchronous Transfer Data Register B (STDB)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The STDA-register buffers the data transferred over the synchronous transfer channel A.
MTDA7 to MTDA0 hold the bits 7 to 0 of the respective time slot. MTDA7 (MSB) is the
bit transmitted/received first, MTDA0 (LSB) the bit transmitted/received last over the
serial interface.
4.6.18 Synchronous Transfer Receive Address Register A (SARA)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The SARA-register specifies for synchronous transfer channel A from which input
interface, port and time slot the serial data is extracted. This data can then be read from
the STDA-register.
ISRA
MTRA6..0
Semiconductor Group
bit 7
bit 7
MTDB7
ISRA
MTDB6
MTRA6
Interface Select Receive for channel A.
0… selects the PCM-interface as the input interface for synchronous
1… selects the CFI-interface as the input interface for synchronous
number at the interface selected by ISRA according to tables 16 and 17:
MTRA6..0 = MA6..0.
P-Transfer Receive Address for channel A; selects the port and time slot
H
H
channel A.
channel A.
MTDB5
MTRA5
MTDB4
MTRA4
149
MTDB3
MTRA3
read/write
read/write
read/write
read/write
Detailed Register Description
MTDB2
MTRA2
address: 04
address: 08
address: 05
address: 0A
MTRA1
MTDB1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
MTDB0
MTRA0
01.96