pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 326

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

5.7.1
Synchronous Transfer Data
Register A
STDA:
The STDA register buffers the data transferred over the synchronous transfer channel A.
MTDA7 to MTDA0 hold the bits 7 to 0 of the respective timeslot. MTDA7 (MSB) is the bit
transmitted/received first, and MTDA0 (LSB) the bit transmitted/received last over the
serial interface.
Synchronous Transfer Receive
Address Register B
STDB:
The STDB register buffers the data transferred over the synchronous transfer channel B.
MTDB7 to MTDB0 hold the bits 7 to 0 of the respective timeslot. MTDB7 (MSB) is the bit
transmitted/received first, MTDB0 (LSB) the bit transmitted/received last over the serial
interface.
Synchronous Transfer Receive
Address Register A
SARA:
The SARA register specifies for synchronous transfer channel A from which input
interface, port, and timeslot the serial data is extracted. This data can then be read from
the STDA register.
ISRA:
MTRA6 … 0:
Semiconductor Group
Registers Used in Conjunction with the Synchronous Transfer Utility
bit 7
bit 7
MTDB7 MTDB6 MTDB5 MTDB4 MTDB3 MTDB2 MTDB1 MTDB0
bit 7
ISRA
MTDA7
Interface Select Receive for channel A; selects the PCM interface
(ISRA = 0) or the CFI (ISRA = 1) as the input interface for
synchronous channel A.
timeslot number at the interface selected by ISRA according to
figure 84: MTRA6 … 0 = MA6 … 0.
P Transfer Receive Address for channel A; selects the port and
MTRA6 MTRA5 MTRA4 MTRA3 MTRA2 MTRA1 MTRA0
MTDA6
MTDA4
326
read/write reset value:
read/write reset value:
read/write reset value:
MTDA3
MTDA2
MTDA1
Application Hints
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PEB 20550
PEF 20550
bit 0
bit 0
bit 0
MTDA0
01.96