pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 76

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

This feature is enabled by setting the RC- (receive check) bit in RLCR and programming
the maximum frame length via bits RL6…RL0.
According to the value written to RL6…RL0, the maximum receive length can be
adjusted in multiples of 32-byte blocks as follows: max. frame length = (RL + 1)
All frames exceeding this length are treated as if they have been aborted from the
opposite station, i.e. the CPU is informed via a
– RME-interrupt, and the
– RAB-bit in RSTA register is set (clock mode 0 - 2)
To distinguish between frames really aborted from the opposite station, the receive byte
count (readable from registers RBCH, RBCL) exceeds the maximum receive length (via
RL6…RL0) by one or two bytes in this case.
2.2.7.6 Serial Interface
Clock Modes
The SACCO uses a single clock for transmit and receive direction. Three different clock
modes are provided to adapt the serial interface to different requirements.
Clock Mode 0
Serial data is transferred on RxD/TxD, an external generated clock (double or single
data rate) is forwarded via pin HDC.
Clock Mode 1
Serial data is transferred on RxD/TxD, an external generated clock (double or single
data rate) is forwarded via pin HDC. Additionally a receive/transmit strobe provided on
pin HFS is evaluated.
Clock Mode 2
This operation mode has been designed for applications in time slot oriented PCM-
systems. The SACCO receives and transmits only during a certain time slot of
programmable width (1 … 256 bits) and location with respect to a frame synchronization
signal, which must be delivered via pin HFS.
The position of the time slot can be determined applying the formula in figure 42.
TSN: Defines the number of 8 bit time slots between the start of the frame (HFS edge)
CS: Additionally a clock shift of 0 7 bits can be defined using register bits
Semiconductor Group
and the beginning of the time slot for the HDLC channel. The values for TSN are
written to the registers TSAR:7 2 and TSN:7 2.
TSAR:RSC2…1, TSAX:XCS2 1 and CCR2:XCS0, CCR2:RCS0.
76
Functional Description
PEB 20550
PEF 20550
01.96
32.