pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 243

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

Memory Access Time
Writing to MACR starts a memory write or read operation which takes a certain time.
During this time no further memory accesses may be performed i.e. the MADR, MAAR,
and MACR registers may not be written. The STAR:MAC bit indicates whether a memory
operation is still in progress (MAC = 1) or already completed (MAC = 0) and should
therefore be interrogated before each access.
Since memory operations must be synchronized to the ELIC internal bus which is
clocked by the reference clock (RCL), the time required for an indirect register access
can be given as a multiple of RCL clock cycles. A ‘normal’ access to a single memory
location, for example, takes a maximum of 9.5 RCL cycles which is approximately 2.4 s
assuming a 4 MHz clock (e.g. CFI configured as standard IOM-2 interface).
Memory Access Modes
Access to memory locations is furthermore influenced by the operation mode set via the
Operation Mode Register OMDR. There are 4 modes which can be selected with the
OMDR:OMS1, OMS0 bits:
Operation Mode Register
OMDR
– The CM reset mode (OMS1 … 0 = 00) is used to reset all locations of the control
– The CM initialization mode (OMS1 … 0 = 10) allows fast programming of the
– In the normal operation mode (OMS1 … 0 = 11) the CFI and PCM interfaces are
Semiconductor Group
memory code and data fields with a single command within only 256 RCL cycles. A
typical application is resetting the CM with the command MACR = 70
the contents of MADR (XX
(unassigned channel) to all code field locations. A CM reset should be made after
each hardware reset. In the CM reset mode the ELIC does not operate normally i.e.
the CFI and PCM interfaces are not operational.
Control Memory since each memory access takes a maximum of only 2.5 RCL cycles
compared to the 9.5 RCL cycles in the normal mode. Accesses are performed on
individual addresses specified by MAAR. The initialization of control/signaling
channels in IOM or SLD applications can, for example, be carried out in this mode
(see chapter 5.5.1). In the CM initialization mode the ELIC does also not work
normally.
operational. Memory accesses performed on single addresses (specified by MAAR)
take 9.5 RCL cycles. An initialization of the complete data memory tristate field takes
1035 RCL cycles.
bit 7
OMS1
OMS0
PSB
H
) to all data field locations and the code ‘0000’
read/write
PTL
243
COS
reset value:
MFPS
Application Hints
CSB
H
00
PEB 20550
PEF 20550
which writes
H
bit 0
RBS
01.96