pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 273

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

5.4.3.2 PCM - PCM Loops
For looping back a timeslot of a PCM input port to a PCM output port, two connections
must be programmed:
The first connection switches the downstream PCM timeslot to a spare CFI timeslot. This
connection is programmed like a normal PCM to CFI link, i.e the MADR contains the
encoding for the downstream PCM timeslot (U/D = 0) which is written to the downstream
CM (MAAR contains the encoding for the downstream CFI timeslot (U/D = 0)). If the data
should also be transmitted at DD# (transparent loop), the programming is performed with
MACR:CMC3 … 0 = 0001 … 0111, the actual code depending on the required
bandwidth. If DD# should be disabled (non-transparent loop), the programming is
performed with MACR:CMC3 … 0 = 0000, the code for unassigned channels.
The second connection switches the serial CFI timeslot data back to the upstream PCM
timeslot. This connection is programmed by writing the encoded PCM timeslot via MADR
to the upstream CM. This “upstream” pointer must however have the MSB set to 0 (U/
D = 0). This MADR value is written to the same spare CFI timeslot as the PCM timeslot
had been switched to in the first step. Only that now the upstream CM is accessed
(MAAR addresses the upstream CFI timeslot (U/D = 1)).
In contrast to the CFI
CFI data out of the upstream data memory (see chapter 5.4.3.1), the PCM
PCM loop is realized differently:
The downstream PCM
downstream serial CFI output. From this internal output, the data is switched to the
upstream serial CFI input if the control memory of the corresponding upstream CFI
timeslot contains a pointer with a leading 0 (U/D = 0). However, this pointer (with U/
D = 0) still points to the upstream data memory, i.e to an upstream PCM timeslot.
The following example illustrates the necessary programming steps for establishing
PCM to PCM loops:
Example
In PCM mode 1 and CFI mode 0 the following non-transparent PCM to PCM loop via CFI
port 1, timeslot 4 shall be programmed:
Downstream: CFI port 1, timeslot 4, bits 7 … 0 from PCM port 0, timeslot 13, bits 7 … 0
W:MADR
W:MAAR
W:MACR
Semiconductor Group
= 0001 1001
= 0001 0010
= 0111 0000
PCM
B
B
B
CFI connection switches the PCM data to the internal
PCM timeslot encoding (pointer to downstream DM)
CFI timeslot encoding (address of downstream CM)
CM code for unassigned channel (0000)
CFI loop, which is internally realized by extracting the
273
Application Hints
PEB 20550
PEF 20550
CFI
01.96