pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 53

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

The SACCO consists of the following logical blocks:
Figure 25
SACCO-Block Diagram (one channel)
2.2.7.2 Parallel Interface
All registers and the FIFOs are accessible via the ELIC parallel P-interface. The chip
select signal CSS selects the SACCO for read/write access. The FIFOs allocate an
address space of 32 bytes each. The data in the FIFOs can be managed by the CPU-
or a DMA-controller.
To enable the use of block move instructions, the top of FIFO-byte is selected by any
address in the reserved range.
Semiconductor Group
CSS
TxD# TSC# CxD#
XFIFO
WR
ELIC Parallel Interface
Protocol Support
Serial Interface
RD
R
53
ALE
AD 0-7
RFIFO
RxD#
INT
ITB05824
Functional Description
DRQR
DRQT
DACKN
HDC
HFS
PEB 20550
PEF 20550
01.96