pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 285

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

PEB 20550
PEF 20550
Application Hints
5.5.1
Initialization of Preprocessed Channels
The initialization of preprocessed channels is usually performed after the CM reset
sequence during device initalization. Resetting the CM sets all CFI timeslots to
unassigned channels (CM code ‘0000’). The initialization of preprocessed channels
consists of writing appropriate CM codes to those CFI timeslots that should later be
handled by the CS or MF handler.
The initialization or re-initialization of preprocessed channels can of course also be
carried out during the operational phase of the device.
If the CFI shall be operated as a standard IOM-2 interface, for example, the CFI frame
consists of 32 timeslots, numbered from 0 to 31 (see figure 58).
The B channels occupy timeslots 0 and 1 (IOM channel 0), 4 and 5 (IOM channel 1), 8
and 9 (IOM channel 2), and so on. The B channels are normally switched to the PCM
interface and are programmed only if the actual switching function is required.
The monitor, D and C/I channels occupy timeslots 2 and 3 (IOM channel 0), 6 and 7
(IOM channel 1), 10 and 11 (IOM channel 2), and so on. These timeslots must be
initialized in both upstream and downstream directions for the desired functionality. In
order to speed up this initialization, the ELIC can be set into the CM initialization mode
as described in chapter 5.3.2.
There are several options available to cover the different applications like switched D
channel, 6 bit signaling, etc. It should be noted that each pair of timeslots can individually
be set for a specific application and that the up- and downstream directions can also be
set differently, if required.
D-Channel Handling Scheme by SACCO-A and D-Channel Arbiter
This option applies for IOM-2 channels where the even timeslot consists of an 8 bit
monitor channel and the odd timeslot of a 2 bit D channel followed by a 4 bit C/I channel
followed by the 2 monitor handshake bits MR and MX.
The monitor channel is handled by the MF handler according to the selection of
handshake or non-handshake protocol. If the handshake option is selected (IOM-2), the
MF handler controls the MR and MX bits according to the IOM-2 specification. If the no
handshake option is selected (IOM-1), the MF handler sets both MR and MX bits to
logical 1; the MR and MX bit positions can then, if required, be accessed together with
the 4 bit C/I field via the even control memory address.
The information of the D-bits are passed to the arbiter in upstream direction where a
decision is made whether the demanding D-channel is allowed to use the SACCO-A
HDLC controller.
In downstream direction the SACCO-A sends D-channel information on a previously
selected IOM-channel.
Semiconductor Group
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